RegViz: Visualize FIFO Bitfield

Freescale Semiconductor /MKE14Z7 /LPUART2 /FIFO

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Interpret as FIFO

TXOF=0, TXEMPT=0, RXUF=0, TXFLUSH=0, RXFLUSH=0, RXIDEN=000, RXUFE=0, RXEMPT=0, TXFE=0, RXFE=0, RXFIFOSIZE=000, TXOFE=0, TXFIFOSIZE=000

Description

LPUART FIFO Register

Fields

RXFIFOSIZE	Receive FIFO. Buffer Depth 0 (000): Receive FIFO/Buffer depth = 1 dataword. 1 (001): Receive FIFO/Buffer depth = 4 datawords. 2 (010): Receive FIFO/Buffer depth = 8 datawords. 3 (011): Receive FIFO/Buffer depth = 16 datawords. 4 (100): Receive FIFO/Buffer depth = 32 datawords. 5 (101): Receive FIFO/Buffer depth = 64 datawords. 6 (110): Receive FIFO/Buffer depth = 128 datawords. 7 (111): Receive FIFO/Buffer depth = 256 datawords.
RXFE	Receive FIFO Enable 0 (0): Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 1 (1): Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
TXFIFOSIZE	Transmit FIFO. Buffer Depth 0 (000): Transmit FIFO/Buffer depth = 1 dataword. 1 (001): Transmit FIFO/Buffer depth = 4 datawords. 2 (010): Transmit FIFO/Buffer depth = 8 datawords. 3 (011): Transmit FIFO/Buffer depth = 16 datawords. 4 (100): Transmit FIFO/Buffer depth = 32 datawords. 5 (101): Transmit FIFO/Buffer depth = 64 datawords. 6 (110): Transmit FIFO/Buffer depth = 128 datawords. 7 (111): Transmit FIFO/Buffer depth = 256 datawords
TXFE	Transmit FIFO Enable 0 (0): Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 1 (1): Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
RXUFE	Receive FIFO Underflow Interrupt Enable 0 (0): RXUF flag does not generate an interrupt to the host. 1 (1): RXUF flag generates an interrupt to the host.
TXOFE	Transmit FIFO Overflow Interrupt Enable 0 (0): TXOF flag does not generate an interrupt to the host. 1 (1): TXOF flag generates an interrupt to the host.
RXIDEN	Receiver Idle Empty Enable 0 (000): Disable RDRF assertion due to partially filled FIFO when receiver is idle. 1 (001): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 2 (010): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 3 (011): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 4 (100): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 5 (101): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 6 (110): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 7 (111): Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
RXFLUSH	Receive FIFO/Buffer Flush 0 (0): No flush operation occurs. 1 (1): All data in the receive FIFO/buffer is cleared out.
TXFLUSH	Transmit FIFO/Buffer Flush 0 (0): No flush operation occurs. 1 (1): All data in the transmit FIFO/Buffer is cleared out.
RXUF	Receiver Buffer Underflow Flag 0 (0): No receive buffer underflow has occurred since the last time the flag was cleared. 1 (1): At least one receive buffer underflow has occurred since the last time the flag was cleared.
TXOF	Transmitter Buffer Overflow Flag 0 (0): No transmit buffer overflow has occurred since the last time the flag was cleared. 1 (1): At least one transmit buffer overflow has occurred since the last time the flag was cleared.
RXEMPT	Receive Buffer/FIFO Empty 0 (0): Receive buffer is not empty. 1 (1): Receive buffer is empty.
TXEMPT	Transmit Buffer/FIFO Empty 0 (0): Transmit buffer is not empty. 1 (1): Transmit buffer is empty.

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